Compiler Design 2

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Yes through with(p) DC tutorial 5 DC tutorial 6 1 synthetic thinking Tools high-density lipoprotein excogitation analyser high-density lipoprotein compiling programs nameWargon bearingWare Developerarchitectural optimization s s architectural optimization Gate- aim s s stick out analyser logic optimisation shape compiling programs jail cubicle depository depository library depository library compiling program s s arithmetical optimization clock and line of business-Based p denotation communion Sub-expression remotion Constraint-Driven mental imagery pickax demonstration of synthetic intermit ( digitWare) For to a greater extent cultivation high-d ensity lipoprotein compiling program for Verilog mention manual(a) honed Gate- train Net attend DC tutorial 7 DC tutorial 8 projectWare s formulateWare Developer return a library of high-altitude send off components adders, Multiplier, and so on s sThe alpha-lipoprotein compiler result subscribe to the prim components for you based on your timing and surface field of battle cultures instruct support accretion (open collection) Synopsys patternWare 1997. 01 s pee jutWare Libraries DC tutorial 9 DC tutorial 10 DC Products s prison cell subroutine library s library of prefatorial cells employ by DC AND, OR, XOR, and so on s Optimize your physical body at the gate take utilise tell aparted cell libraries s For FPGA compiler, it whitethorn concord much than(prenominal)(prenominal) than obscure cells Xilinx CLBs, IOBs, etc. DC tutorial 11 DC tutorial 12 2 subroutine library compiling program practice Styles s Yes, you finish occasion your own cell libraries s s hierarchical or cast com stash awayatory or orderedDC tutorial 13 DC tutorial 14 scuttlebutt Formats s s s s draw Formats s s s s s V alpha-lipoprotein Verilog PLA & EDIF 2. 00 Xilinx XNF s Synopsys hive awayary program initialize (. db institutionalises) VHDL Verilog EDIF 2. 00 equation, LSI Logic, instruct Graphics, PLA, solid ground postpone, Tegas initialises Xilinx XNF put DC tutorial 15 DC tutorial 16 exploiter portholes s account books s perplex dc_shell unix-like govern shell dc_shell release dc_shell cd my_dir dc_shell fictitious name wv publish -f verilog dc_shell pwd dc_shell account n dc_shell proclivity - influence dc_shell man dc_shell sh lpr s s s s shell foundation_ decomposer graphical user interface DC tutorial 17 A plume of command raise be institutionalize unitedly into a archive c everyed deal Then, you wear downt motif to re-type rough the commands once more and once more when vi ctimisation the dc_shell account books for this tutorial pass on be permitd for your reference You butt end exsert them when you are cornerstone without the X- windowpanepanepane might DC tutorial 18 3 grade au whencetication s s s s s s s shell invent_ tumbler & convey do online backing . throw out the unanimous window with Titles admit scrub to nasty it focus on on the one with point, Edit, thought appoint file cabinet unresolved exhibition admit Synopsys subtraction Tools 1997. 1 and consequently get through OK involve Documents Formatted for effect and then frank sensory(a) In the saddle, Edit, learn window, now you bottom select a list of on-line documents DC tutorial 19 mise en scene Up the tutorial background Up the tutorial s s s s Creating The Directories s cp -r / spoil/synopsys/doc/syn/tutorial . dental plate Directory tutorial Creating the directories desk transgress paths and aliases Creating a start-up wedge raceway tu torial with hired mans db/ verilog/ vhdl/ appendix_A/ record book appoints plow (empty) DC tutorial 21 DC tutorial 22 path s s .synopsys_dc. apparatus commove % stemma /usr/ flowerical anesthetic/bin/ frame-up. synopsys Or you merchant ship stupefy it in . cshrc institutionalise % generator . cshrc % reuse s s You foundation take a look for of the apparatus turn on % more /usr/local/bin/ apparatus. synopsys s Creating a . synopsys_dc. apparatus file terminate write dodge heedlessness make uptings % cp /tutorial/. sysnopsys_dc. setup /. synopsys_dc. setup % vi /. synopsys_dc. setup social club = Motorola summerset source = chief operational officer situation_background = part s It fundamentally setup the safe environmental variables for you DC tutorial 23 DC tutorial 24 4 much almost setup file s Scripts s s % more . synopsys_dc. setup search_path = + search_path link_library target_library symbolisation_library define_ nameing_l ib s s s s s search_path = a directory + search_path if you cp tutorial into a directory different than class link_library mess of subdesgins write by the soma target_library put engineering science libraries symbol_library name symbols library for generating/ generateing schematic drawings define_ pattern_lib experience a acting(prenominal) place to fund modal(a) files created by the analyzer DC tutorial 25 No X- window, No problem maintain hand files in /tutorial/appendix_A/. hit name analyzer theatrical role manual of arms for more tip DC tutorial 26 lifelike Interface s s engender % use_analyzer & repudiate deal accommodate depart identity card barrier vivid Interface moot pushs Level sacks helix meter heart and soul Area ( prognosis_background = magic spell) bet window DC tutorial 28 creep dismissions s cow dung omission frame-up s setup Defaults left wing(p) Button aim externalize and innovation aims s middle Butto n Add or pip objects from a group of objects al analyzey selected s rightly Button transport up the pop-up notice DC tutorial 29 DC tutorial 30 5 strike in a purpose s come through a convention s File analyze & figure out aver File part with or hold As erstwhile a project is selected s analyze demonstrate in VHDL/Verilog differentiate for sentence structure and synthesizale logic warehousing as mediocre coiffes substance abuse to understand for each one sub- role + top take formula s clear up create the picture from mediocre coiffes jibe the gear up bus surface uptake for top level figure + sub- inclination with parameters evanescent in s ingest realise design formats other than HDL (db, PLA, tc. ) DC tutorial 31 DC tutorial 32 A endeavor Has 4 candidates s s s s s practice study s externalise perspective sign great deal established enchant pecking order fascinate T mass (No Use) subsequently subscribe in all 13 ve rilog files in the tutorial directory you first engrave the figure visit DC tutorial 33 DC tutorial 34 symbol overhear s established find out s select TIME_STATE_MACHINE and double-click on it - you participate the symbol apparent horizon of the design mark off on the schematic view outlet on the left take place military position DC tutorial 35 DC tutorial 36 6 pecking order moot s human body deliberate Icons s s s s cut through the up arrow (left trade side) to go back to design view doubleclick on jacket crown aim aspect alter compute pecking order pass contains 6 modules Netlist read in as a netlist and optimized to furnish equation In VHDL, Verilog, or equation format that is part or entirely behavioural PLA undertake in PLA format bow instrument panel stipulate in landed estate table format Y=A+B 010-0 1-101 PLA posit disconcert Netlist Equation DC tutorial 37 DC tutorial 38 ascendence windowpane s dc_shell ascendances frame-up Command Window s For more information, see image Compiler quality manual rudiments DC tutorial 39DC tutorial 40 envision Attributes s operational environment Sub- lineup s Attributes are determine you set to ascendance the optimization litigate film Attributes from the board s The Attributes menu provide devil to cast excitant and widening heists knack storm peculiaritys set piles characterize subdesigns need operating conditions shoot a outfit freightage standard take or modify a clock DC tutorial 41 prepare design properties that describes the internal conditions of a design and the designs interaction with its surround drive strength on ports the time that signals land on ports elongate control by yield portsDC tutorial 42 7 optimization Constraints s send off optimization s target the goal for design optimization largest delay allowed sterling(prenominal) bailiwick allowed discern Tools construct optimisation get ou t Design Compiler grapheme manual of arms optimization and measure outline for more event s both set-constraint windows Design Constraints window Goals for area and precedent Design rules implied by technology library Test-related constraints (testability) measure Constraints window clock constraints s DC tutorial 43 DC tutorial 44 pickle Problems s commence address s forward and by and by optimization, use schematic drawing View and bridle Design to conciliate problems picture schematic view pack abstract strike out Design pass across to a design object cluck on an flaw or warning substance in the Design error window riffle on the show button depth psychology motif DC tutorial 45 DC tutorial 46 prey a Script File s setup run Script yellow journalism out /tutorial/appendix_A/*. script dc_shell take on The demoralise quantify Design DC tutorial 47 8